\subsection{Synthesis of domain-specific accelerators}
As part of our experiments, we synthesized a sample accelerator that computes the Euclidean distance between two vectors. 
This accelerator can be employed in feature-matching algorithms, where the Euclidean distance between a test feature descriptor vector (such as those obtained from algorithms like SIFT or SURF) and every feature vector from the training database is computed for recognition tasks. The input consists of 64-dimensional vectors, each element being 16 bits in width. The accelerator consists of of an 8-stage pipelined execution unit consisting of an array of multipliers and adders that compute the sum of squares of element-wise difference between a pair of vectors. 
The accelerator HDL code was simulated and verified using Synopsys VCS~\cite{vcs}. 
The designs were synthesized using the in-house HTFET standard cell library, using Synopsys Design Compiler~\cite{dcshell2010}.

Figure~\ref{fig:euclidean-dist-ckt} shows the block diagram corresponding to an accelerator for computing Euclidean distance between two vectors.

\begin{figure}[!ht]
	\centering
	\epsfig{file=figs/euclidean_dist_ckt.eps, angle=0, width=1\linewidth, clip=}
	\caption{Block diagram for computation of Euclidean distance}
	\label{fig:euclidean-dist-ckt}
\end{figure}

The overall execution time includes the data transfer time for streaming the input to the accelerator using DMA transfer from external memory and the accelerator computation time for 200 feature vectors in the training database and 1 test vector. 
For an input stream of images, the throughput of the HTFET accelerator was computed to be 19392 frames/second.

\begin{figure}[!ht]
	\centering
	\epsfig{file=figs/accelerator_results.eps, angle=0, width=1.04\linewidth, clip=}
	\caption{Normalized delay, power, energy and EDP of HTFET, iso-performance CMOS and iso-voltage CMOS accelerator designs. All results are normalized w.r.t the HTFET design.}
	\label{fig:accelerator-results}
\end{figure}

\subsection{Comparison with existing CMOS designs}
The salient feature of HTFET based accelerators is their capability to achieve high throughput with energy efficiency even while operating at low supply voltages.
This is evident when the HTFET-based Euclidean distance accelerator was compared with equivalent CMOS designs. 
An iso-voltage CMOS design operating at 0.3V is severely limited by its inherent sub-threshold operation and consequently has a transistor delay that is over 30X higher than HTFET. Hence a TFEET accelerator design is more feasible, even though its total power consumption is higher than the iso-voltage CMOS design due to its far superior switching speed. Consequently, the accelerator is much slower, and can be clocked at less than 100~MHz in order to meet timing constraints.
In order to match the performance of the HTFET accelerator, the CMOS design will have to operate at 0.54V. This increases the power and hence, the energy overheads.
The performance, power, energy and energy-delay product results are summarized in Table~\ref{fig:accelerator-results}.




\begin{comment}
The designs were synthesized using the in-house HTFET std library and the NCSU FreePDK 45~nm standard cell library~\cite{ncsupdk}.
The device supply voltage and capacitances at 45~nm CMOS were scaled in order to correspond to the 22~nm node.
We then determined the maximum frequency for the design in each case, so as to meet critical path timing constraints. 
The difference between the clock frequencies of the CMOS and HTFET designs represented the performance loss due to adoption of the slower HTFET device.
This would be offset by the superior power and energy efficiency of the HTFET accelerator designs.
These results are summarized in Table() and ().


%%%to do
\begin{itemize}
\item Timing numbers
\item Table showing power/ energy/ EDP of CMOS and HTFET
\end{itemize}

\end{comment}


% LocalWords:  HDL HTFET Synopsys CMOS
